A field effect transistor having a metal gate electrode has enhanced performance over a comparable field effect transistor having a polysilicon electrode due to higher conductivity of the gate electrode, and consequently, a reduced signal delay in the operation of the transistor. Further, the polysilicon depletion effect is eliminated by the metal gate electrode, which allows the gate dielectric to be electrically thinner. In addition, boron dopant diffusion into the channel region is eliminated in the case of p-type field effect transistors. While such benefits of the metal gate electrode are known in the art, integration of metal gate electrodes has proven to be difficult to implement in a conventional process flow for complementary metal oxide semiconductor (CMOS) transistors.
Specifically, most metal gate materials interact with a gate dielectric during the high temperature processing steps required for source/drain (S/D) junction activation anneals. The need to keep the metal gate stack from receiving high temperature anneals has lead to the development of the “gate last” or “replacement gate” integration schemes, in which a gate stack is fabricated after source/drain activation and metallization of the source and the drain, and maintained at temperatures below 500° C. during subsequent processing.
The difficulty of integrating metal gate electrodes into a semiconductor structure employing CMOS transistors is further increased because integration of CMOS transistors requires two gate materials, one having a work function near the valence band edge of the semiconductor material in the channel and the other having a work function near the conduction band edge of the same semiconductor material. For example, in CMOS devices having a silicon channel, a conductive material having a work function of about 4.0 eV is necessary for n-type metal oxide semiconductor field effect transistors (NMOSFETs) and another conductive material having a work function of about 5.0 eV is necessary for p-type metal oxide semiconductor field effect transistors (PMOSFETs).
Replacement gate integration schemes known in the prior art typically require formation of the gate dielectric after a source/drain activation anneal. Exposure of a semiconductor surface by etching prior to formation of gate dielectrics, which typically comprise a high-k dielectric material, often leads to interfacial defects between a channel and the gate dielectric. Further, two different metal gate materials are typically formed with accompanying lithographic patterning steps and planarization steps. Many prior art replacement gate integration schemes require two separate steps for formation of gate dielectrics. Thus, while replacement gate integration schemes known in the prior art increase the choice of materials for a metal gate electrode, increases in the processing complexity and cost is substantial over typical conventional CMOS process flows.
In view of the above, there exists a need for a semiconductor structure that provides functional advantages of CMOS transistors with metal gate electrodes including dual work function, while avoiding damages and interfacial states between gate dielectrics and channels.
Further, there exists a need for methods of manufacturing such a semiconductor structure while minimizing any increase in processing complexity and cost over conventional CMOS integration schemes.